A) Field of the Invention
The present invention relates to a semiconductor memory device such as a static random access memory (SRAM) and its test method.
B) Description of the Related Art
A read/write test for memory cores is performed before semiconductor memories such as SRAM are shipped, the memory cores storing binary data of “0” and “1”.
This read/write test for a memory core generates first a test pattern to decide what data is written in which memory core. Next, a write mode is set and an address of a subject memory core is designated. As the address is designated, a corresponding word line and corresponding bit line and inverted bit line are selected, and data determined by the test pattern is written in the designated memory core.
After the data write, a mode is changed to a read mode, the address of the memory core in which data was written is designated, and the data is read. If the write data is coincident with the read data, it is judged that the memory core can be read/written correctly, whereas if not coincident, it is judged that the memory core is defective. For conventional reference documents regarding this application, refer to Japanese Patent No. 3348632, JP-A-HEI-04-344399, JP-A-2001-023400 and JP-A-2001-210095.
Memory cores occupy most of the size of SRAM, and most of defects are formed in the memory cores. Therefore, the test method is desired being capable of inspecting defects of memory cores in a short time. However, a conventional read/write test is required to activate peripheral circuits for memory cores while memory cores are inspected, in order to execute the above-described series of read/write operations.
This series of operations takes a time of several clocks of the operation frequency of SRAM. If memory cores of SRAM are implemented in LSI particularly at a deep logical stage, the number of peripheral circuits to be activated during the test increases, and the test pattern is required to be generated while considering the timings of operating the peripheral circuits. It takes therefore a long time to form a test pattern.